1. Field of the Invention
The present invention relates to a via forming method and a method of manufacturing a multi-chip package using the same, and in particular, to a via forming method and a method of manufacturing a multi-chip package using the same which use a solution containing metal particles.
2. Description of the Related Art
A semiconductor chip includes active elements or passive elements which are connected to each other by various forms of wiring lines. With the Recent improvement in the degree of integration of a package structure with a reduction in the size of electronic products and improvement in the performance of electronic products, multi-chip packages in which multiple semiconductor chips are stacked are being released. In this case, multiple semiconductor chips may be connected to each other by wiring lines.
Wiring lines connect elements on the same level or connects elements on different levels vertically. Wiring lines for a vertical connection may be formed in various ways. Vertical wiring lines in a semiconductor chip may be formed by forming holes in an interlayer insulating layer, depositing a conductive layer to fill the holes, and performing etching so that portions of the conductive layer inside the holes remain. When the conductive layer is formed of copper, damascening is performed instead of etching.
In multi-chip packages, in order to electrically connect semiconductor chips on different levels, wire bonding or vias through semiconductor chips are used. Recently, with an improvement in the degree of integration of packages, wiring using vias is in the limelight. Such via-holes are formed by electroplating, laser reflow, dipping, etc. Since a laser reflow or dipping process needs high-pressure of 5 Mpa or greater while forming via, electroplating is generally used and will be described below in detail.
FIGS. 1 and 2 are cross-sectional views illustrating processes of a via forming method according to the related art.
Referring to FIG. 1, an insulating layer 12 is formed on a semiconductor substrate 10 having an active surface on which electric elements have been formed. Then, patterning on a predetermined area of the semiconductor substrate 10 is performed to form via-holes 11. Subsequently, an insulating layer 14 is formed on the inside surface of the via-holes 11.
Then, a seed layer 16 is formed on the inside surface of the via-holes 11. The seed layer 16 may be formed of copper. Next, copper is deposited on the seed layer 16 by electrolytic copper plating to form vias 18 filling the via-holes 11. In this case, copper is deposited not only in the via-holes 11 but also on the surface of the semiconductor substrate 10, resulting in an over burden layer 20.
Referring to FIG. 2, the over burden layer 20 is removed by a chemical mechanical polishing (CMP) process 22 to expose the vias 18 and the surface of the semiconductor substrate 10. If the vias 18 are formed of another material instead of copper, etching is used to remove an over burden layer 20.
When electroplating according to the related art is used to form the vias 18, the seed layer 16 should be formed inside the via-holes 11, which makes forming of the vias 18 complicated. Moreover, electroplating takes a long time, and forms a seam or a void in the vias 18, which causes an increase in wiring resistance, when the aspect ratio of the via-holes 11 increases.
Also, electroplating involves a separate process for removing the over burden layer 20 such as a CMP process or an etching process mentioned above. In a case of the CMP process, in order to prevent damage to an underlying layer, it is required to additionally form a polishing stop layer on the semiconductor substrate 10 or to accommodate for a process time if there is no polishing stop layer. That is, the above-mentioned process makes forming of vias 18 more complicated.